Initializing scannable and non-scannable latches from a common clock buffer

ABSTRACT

Aspects include a computer-implemented method for initializing scannable and non-scannable latches from a clock buffer. The method includes receiving a clock signal; receiving control signals including a hold signal, a scan enable signal, and a non-scannable latch force signal; responsive to receiving a low input from the hold signal and the scan enable signal, outputting a high signal from a functional clock port on a next cycle; responsive to receiving a high input from the scan enable signal and a low input from the hold signal, outputting a high slave latch scan clock signal on the next cycle; responsive to receiving a high input from the hold signal and the scan enable signal, outputting a high master latch clock signal on the next clock cycle; and responsive to receiving a high input from the non-scannable latch force signal, outputting a low master latch clock signal on a current cycle.

BACKGROUND

The present disclosure relates generally to scannable and non-scannablelatches, and more specifically, to a method, system, and computerprogram product for initializing scannable and non-scannable latchesfrom a common clock buffer.

Semiconductor chips containing digital logic contain a variety ofsequential memory logic elements that are clocked in local synchronousgroups by a controllable local clock buffer circuit. The local clockbuffer circuit is connected to a global clock grid or clock tree.Different latch types are clocked by different local clock buffersdepending on their type. When new latch types are added to a region onthe semiconductor chip, the latches are installed along with a localclock buffer circuit. This additional local clock buffer circuitconsumes additional power, occupies additional area, and adds additionalcapacitive load points to the global clock grid or global clock tree.

SUMMARY

According to embodiments, a system for initializing scannable andnon-scannable latches from a common clock buffer is described. Thesystem includes a processor, coupled to a memory, configured to performa method, the method comprising: receiving a clock signal into a localclock buffer; receiving, at each clock signal, a set of control signals,the set of control signals including a hold control signal, a scanenable control signal, and a non-scannable latch force control signal;responsive to receiving a low input from the hold control signal and thescan enable control signal, outputting a high signal from a functionalclock port on the local clock buffer on a next clock cycle; responsiveto receiving a high input from the scan enable control signal and a lowinput from the hold control signal, outputting a high slave latch scanclock signal on the next clock cycle; responsive to receiving a highinput from the hold control signal and the scan enable control signal,outputting a high master latch scan clock signal on the next clockcycle; and responsive to receiving a high input from the non-scannablelatch force control signal, outputting a low master latch scan clocksignal on a current clock cycle.

In accordance with an embodiment of the invention, a method forinitializing scannable and non-scannable latches from a common clockbuffer is described. The method includes receiving a clock signal into alocal clock buffer; receiving, at each clock signal, a set of controlsignals, the set of control signals including a hold control signal, ascan enable control signal, and a non-scannable latch force controlsignal; responsive to receiving a low input from the hold control signaland the scan enable control signal, outputting a high signal from afunctional clock port on the local clock buffer on a next clock cycle;responsive to receiving a high input from the scan enable control signaland a low input from the hold control signal, outputting a high slavelatch scan clock signal on the next clock cycle; responsive to receivinga high input from the hold control signal and the scan enable controlsignal, outputting a high master latch scan clock signal on the nextclock cycle; and responsive to receiving a high input from thenon-scannable latch force control signal, outputting a low master latchscan clock signal on a current clock cycle.

In accordance with another embodiment of the invention, a computerprogram product for clocking scannable and non-scannable latches from acommon clock buffer is described. The computer program product comprisesa computer readable storage medium having program instructions embodiedtherewith, the program instructions executable by a processor located ona device to cause the computer processor to perform a method. The methodincludes receiving a clock signal into a local clock buffer; receiving,at each clock signal, a set of control signals, the set of controlsignals including a hold control signal, a scan enable control signal,and a non-scannable latch force control signal; responsive to receivinga low input from the hold control signal and the scan enable controlsignal, outputting a high signal from a functional clock port on thelocal clock buffer on a next clock cycle; responsive to receiving a highinput from the scan enable control signal and a low input from the holdcontrol signal, outputting a high slave latch scan clock signal on thenext clock cycle; responsive to receiving a high input from the holdcontrol signal and the scan enable control signal, outputting a highmaster latch scan clock signal on the next clock cycle; and responsiveto receiving a high input from the non-scannable latch force controlsignal, outputting a low master latch scan clock signal on a currentclock cycle.

Additional features and advantages are realized through the techniquesof the invention. Other embodiments and aspects of the invention aredescribed in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with theadvantages and the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other features and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram illustrating one example of a processingsystem for practice of the teachings herein;

FIG. 2 is a circuit diagram for initializing scannable and non-scannablelatches from a common clock buffer in accordance with one or moreembodiments;

FIG. 3 is a timing diagram illustrating a method for initializingscannable and non-scannable latches from a common clock buffer inaccordance with one or more embodiments;

FIG. 4 is a block diagram of an electronic scannable latch in accordancewith one or more embodiments; and

FIG. 5 is a block diagram of a method for initializing scannable andnon-scannable latches from a common clock buffer according to one ormore embodiments.

DETAILED DESCRIPTION

In accordance with embodiments of the disclosure, a method and apparatusfor initializing scannable and non-scannable latches from a common clockbuffer is provided. Typically, scannable latches cannot share a localclock buffer with non-scannable latches because the initializationclocks for the non-scannable latches would erase the scan initializationdata for the scannable latches. This forces extra initialization localclock buffers and overhead in chip areas where scannable andnon-scannable latches are desired. Embodiments described herein includea local clock buffer circuit that receives several control inputsincluding a hold control signal, a scan enable control signal, and anon-scannable latch force control signal. The local clock buffer isconnected to the global or grid clock originating from a computersystem. The local clock buffer outputs three clock signals including anL1 latch scan clock, an L2 latch scan clock, and a functional clock.These local clock buffer outputs are coupled to scannable latch clockinputs within the computer system. The scannable latches are configuredas a L1 latch and a two-port L2 latch. Additionally, the functionalclock output is coupled to the non-scannable latch functional clockport. Based upon the control inputs, the local clock buffer, followingthe method taught herein, can initialize the scannable latches and fillthe non-scannable latches. The non-scannable latch force control signalis inputted into the local clock buffer. The local clock buffer isconfigured to receive this non-scannable latch force control signal andwhen the signal is high, this forces the local clock buffer output forthe L1 latch scan clock to be low.

Referring to FIG. 1, there is shown an embodiment of a processing system100 for implementing the teachings herein. In this embodiment, thesystem 100 has one or more central processing units (processors) 101 a,101 b, 101 c, etc. (collectively or generically referred to asprocessor(s) 101). In one embodiment, each processor 101 may include areduced instruction set computer (RISC) microprocessor. Processors 101are coupled to system memory 114 and various other components via asystem bus 113. Read only memory (ROM) 102 is coupled to the system bus113 and may include a basic input/output system (BIOS), which controlscertain basic functions of system 100.

FIG. 1 further depicts an input/output (I/O) adapter 107 and a networkadapter 106 coupled to the system bus 113. I/O adapter 107 may be asmall computer system interface (SCSI) adapter that communicates with ahard disk 103 and/or tape storage drive 105 or any other similarcomponent. I/O adapter 107, hard disk 103, and tape storage device 105are collectively referred to herein as mass storage 104. Operatingsystem 120 for execution on the processing system 100 may be stored inmass storage 104. A network adapter 106 interconnects bus 113 with anoutside network 116 enabling data processing system 100 to communicatewith other such systems. A screen (e.g., a display monitor) 115 isconnected to system bus 113 by display adapter 112, which may include agraphics adapter to improve the performance of graphics intensiveapplications and a video controller. In one embodiment, adapters 107,106, and 112 may be connected to one or more I/O busses that areconnected to system bus 113 via an intermediate bus bridge (not shown).Suitable I/O buses for connecting peripheral devices such as hard diskcontrollers, network adapters, and graphics adapters typically includecommon protocols, such as the Peripheral Component Interconnect (PCI).Additional input/output devices are shown as connected to system bus 113via user interface adapter 108 and display adapter 112. A keyboard 109,mouse 110, and speaker 111 all interconnected to bus 113 via userinterface adapter 108, which may include, for example, a Super I/O chipintegrating multiple device adapters into a single integrated circuit.

In exemplary embodiments, the processing system 100 includes a graphicsprocessing unit 130. Graphics processing unit 130 is a specializedelectronic circuit designed to manipulate and alter memory to acceleratethe creation of images in a frame buffer intended for output to adisplay. In general, graphics processing unit 130 is very efficient atmanipulating computer graphics and image processing and has a highlyparallel structure that makes it more effective than general-purposeCPUs for algorithms where processing of large blocks of data is done inparallel.

Thus, as configured in FIG. 1, the system 100 includes processingcapability in the form of processors 101, storage capability includingsystem memory 114 and mass storage 104, input means such as keyboard 109and mouse 110, and output capability including speaker 111 and display115. In one embodiment, a portion of system memory 114 and mass storage104 collectively store an operating system to coordinate the functionsof the various components shown in FIG. 1. The system 100 can beimplemented in order to perform the testing of various semiconductorsand IC devices.

FIG. 2 illustrates a circuit diagram for initializing scannable andnon-scannable latches from a common clock buffer according to anexemplary embodiment. The circuit diagram 200 includes a local clockbuffer 202, three electronic scannable latches 204, and a non-scannablelatch 206. While only three electronic scannable latches 204 and onenon-scannable latch 206 are shown in FIG. 2, in one or more embodiments,any number of combinations of these latch types can be utilized.

In one or more embodiments, the local clock buffer 202 has the followinginput ports: a global or grid clock port (GCK), a scan enable port (SE),a scan latch hold port (SL_HLD), a non-scan latch hold port (NSL_HLD),and a non-scannable latch force port (NSL_FCE). Each of these ports forthe local clock buffer 202 is configured to receive a control signal. Inan embodiment, the scannable latch hold port (SL_HLD) and thenon-scannable latch hold port (NSL_HLD) are the inputs to an AND gate,so that if either the SL_HLD or the NSL_HLD or both have a low controlsignal, the resultant would be a low signal. If both the NSL_HLD andSL_HLD receive a high control signal, the resultant would be a highsignal. In an embodiment, the NSL_HLD and SL_HLD can be substituted witha hold input signal HLD. In one or more embodiments, the scannable latchhold port (SL_HLD) and the non-scannable latch hold port (NSL_HLD) canbe inputs to any number of digital logic gates before inputting into thelocal clock buffer.

In one or more embodiments, the non-scannable latch force (NSL_FCE) portis configured to receive a non-scannable latch force (NSL_FCE) controlsignal. The NSL_FCE control signal, when high, will force the L1 scanclock (SDCK) to low. In one or more embodiments, the NSL_FCE port can beinputted into any combination of digital logic gates such as, forexample, a two port OR gate where the NSL_FCE control signal is inputtedinto a first port of the OR gate and the invert of the scan enable (SE)control signal can be inputted into a second port of the OR gate.

In one or more embodiments, the local clock buffer 202 has the followingoutput ports: a function clock port (LCK) and two scan clock ports thatoutput a master latch or L1 latch scan clock signal (SDCK) and a slavelatch or L2 latch scan clock signal (SLCK). In the illustrativeembodiment, the SDCK and the SLCK ports are coupled to each of theelectronic scannable latches 204 at their corresponding SDCK port andSLCK ports. The LCK port for the local clock buffer 202 is coupled tothe corresponding LCK ports of both the scannable 204 and non-scannablelatch 206 and it drives the functional clock that facilitates the inputof functional data into the respective latches. In an embodiment, theelectronic scannable latches 204 are configured as a master slave latchor L1 and L2. An illustrative embodiment of the L1 and L2 latches withinthe scannable latches 204 are described in FIG. 4. The SDCK drives themaster or L1 latch and the SLCK drives the slave or L2 latch. In anembodiment, the SDCK and the SLCK are generally orthogonal clocks unlessSDCK is forced to a low state or “0” by the combination of controlsignals NSL_FCE=“1” or SE=“0”.

In one or more embodiments, the global or grid clock input (GCK) isreceived from a free running clock which inputs into the global clockport (GCK) of the local clock buffer 202. The scan enable port (SE)receives a control signal that will allow for outputting a scan clocksignal from either the SDCK or the SLCK ports. For example, when thescannable latches 204 are in scan mode, the scan enable port (SE) willreceive a high control signal input which will then allow, subject tothe other control signals, for the scan clocks (SDCK and SLCK) to outputa high signal. However, if the scan enable port (SE) receives a lowcontrol signal input, the scan clocks will be low and the functionalclock port (LCK) of the local clock buffer 202 can be enabled, subjectto the other control signals, to output a high signal. The scan enable(SE) port allows for a scan data-in operation for the scannable latches204.

In one or more embodiments, the scannable latches 204 contain a port foreach of the three clocks: the scan clock for the master latch (SDCK),the scan clock for the slave latch (SLCK), and the functional clock(LCK). In addition, the scannable latches 204 contain ports for scan-indata (SI) and for function data (D). The scannable latches 204 contain aport for scan-out data (SO). In the illustrative embodiment, thescannable latches 204 are arranged in a scan chain configuration;however, other configurations for the scannable latches may be utilized.

In one or more embodiments, the non-scannable latch 206 contains a portfor the functional clock signal (LCK) and a function port (D). Thenon-scannable latch 206 may be a D-flip flop or any other type ofnon-scannable latch known in the art.

FIG. 3 illustrates a timing diagram illustrating a method forinitializing scannable and non-scannable latches from a common clockbuffer according to one or more embodiments. The timing diagram includesthe GCK 302 which, as mention above, is the free running grid clock.Each letter within the columns following the GCK 302 represents a clockcycle. For example, A represents one clock cycle while B would representthe following clock cycle and so on and so forth. Next, the NSL_HLD 304which, as mention above, is the non-scannable latch hold control signaland the following columns represent its state at each clock cycle. Theremaining control signals are the SL_HLD 306 (scannable latch hold), theSE 308 (scan enable), and the NSL_FCE 310 (non-scannable latch force).The timing diagram 300 illustrates three outputs for the local clockbuffer 202 which include the LCK 312 which, as mention above, is thefunctional clock output, the SDCK 314 (master latch or L1 scan clockoutput), and the SLCK 316 (slave latch or L2 scan clock output).

In one or more embodiments, the scan initialization begins at clockcycle A and completes at clock cycle X. The timing diagram shows a scaninitialization for the three scannable latches 204 and the onenon-scannable latch 206 from FIG. 2. As shown in clock cycle A, the scanclock for the master or L1 latch (SDCK) 312 has a high output whichdrives the scan clock for the master or L1 latch of the first in theseries of scannable latches 204 from FIG. 2. While the SDCK 312 is high,scan data is inputted into the L1 latch of the first in the series ofscannable latches 204. On the third clock cycle, cycle C, the SL_HLD 306(scan latch hold input) drops to a low input. On the following clockcycle, cycle D, the scan clock for the slave or L2 latch 316 (SLCK) goeshigh. On cycle D, the SLCK goes high and the scan data from the L1 latchtransfers to the L2 latch which is referred to as a scan operation. Atclock cycle D, the scan operation has been performed for the first inthe series of three scannable latches as illustrated in FIG. 2. Whileonly three scannable latches 204 are displayed in FIG. 2, more or lessthan three can be utilized for the practicing of the invention herein.

In one or more embodiments, the scan operation from clock cycles A-D isrepeated for the next four clock cycles where the SLCK goes high againon cycle H. When the SLCK goes high on cycle H, the scan data isinputted into the L2 latch of the second in the series of threescannable latches. On the next clock cycle, cycle I, the SDCK is highfor two more cycles; however, at clock cycle K, the non-scan latch forcecontrol signal (NSL_FCE) 310 goes high and the SDCK goes low on the sameclock cycle K. At the same time, on clock cycle K, the SL_HLD 306 goeslow allowing for the SLCK to go high on the next clock cycle, cycle L,for the last scan operation for the three scannable latches 204. TheNSL_FCE port on the local clock buffer 202 is configured to receive acontrol signal wherein if the control signal is high, it forces the SDCK314 output to be low and overrides the other control signals to causethe SDCK 314 output to be low. When the NSL_FCE 310 control signal islow, it no longer forces the SDCK 314 output to be low and the SDCK 314output is controlled by the other control signals for the local clockbuffer 202.

In one or more embodiment, the non-scannable latch fill operation forthe non-scannable latch 206 is performed on clock cycle P in the timingdiagram 300. Beginning with clock cycle K, the scan clock for the L1 ormaster latch 314 (SDCK) is forced to low, while the NSL_FCE 310 is high.While the SDCK 314 is low, scan data is held in the master or L1 latch.The final scan operation is performed when the SL_HLD 306 goes low andthe following clock cycle, cycle L, the slave or L2 latch scans in thescan data. On clock cycle N, the scan enable (SE) 308 control signalgoes low. While the scan enable (SE) 308 is low, the NSL_HLD 304(non-scan latch hold) control signal goes low, on Cycle O, which allowsfor the functional clock output 312 (LCK) to go high on the next clockcycle, cycle P. With the functional clock 312 high, the scan data heldin the L2 latch of each of the scannable latches 204 is destroyed.However, the master or L1 latch scan clock (SDCK) 314 has remained lowallowing the scan data in the master or L1 latch to be preserved. Next,the scan enable (SE) 308 goes high on clock cycle R. The SDCK 314remains low and, at cycle S, the non-scannable latch hold (NSL_HLD) 304goes low which allows the slave or L2 latch scan clock (SLCK) 316 to gohigh on the next clock cycle, cycle T. In one or more embodiments, theNSL_HLD is dropped to a low state at clock cycle O instead of the SL_HLDto avoid firing a clock signal from other local clock buffers that arecoupled to and drive only scannable latches and are not needed to fire.When the SLCK 316 goes high on cycle T, the scan data that was preservedin each of the master or L1 latches is scanned back into each of theslave or L2 latches. Next, at clock cycle U, the NSL_FCE 310 goes backto a low state thus allowing the SDCK to go back to a high state.

In the illustrative embodiment, the scan operation occurs every fourthclock cycle as shown in the timing diagram 300. However, the scanoperation can occur on any number of clock cycles. For example, the scanoperation can occur every second clock cycle or every eighth clockcycle.

FIG. 4 illustrates a block diagram of an electronic scannable latchaccording to one or more embodiments. The scannable latch 204 contains amaster or L1 latch 410 and a slave or L2 latch 412. Master latch and L1latch can be used interchangeably. In addition, slave latch and L2 latchcan be used interchangeably herein. The L1 latch 410 is a one-port latchthat is configured to receive scan-in data 404 into its scan in port(SI). The L1 latch is driven by the L1 latch scan clock (SDCK) 314. TheL1 latch 410 has a clock port 416 which is configured to receive the L1latch scan clock signal (SDCK) 314. The L1 latch 410 contains a scan outport (SO) which is coupled to the scan in port (SI) of the L2 latch 412.The L2 latch is a two-port latch containing a scan-in port (SI) and afunction data port (D). These ports are configured to receive scan-outdata from the L1 and function data 402. The L2 has two clock ports: a L2latch scan clock port 418 and a functional clock port 414. These portsare configured to receive the L2 latch scan clock signal 316 and thefunctional clock signal 312. The L2 latch 412 contains a scan out port(SO) which is configured to output scan out data 406. The SDCK 314, SLCK316, and the LCK 312 input signals are received from the respectiveoutput ports of the local clock buffer 202.

Referring back to the timing diagram 300 of FIG. 3, the SDCK 314 is highfor the first three clock cycles (cycles A-C) which inputs the scan-indata 404 into the L1 latch 410. The SLCK 316 goes high on clock cycle D,which pushes the scan data from the L1 latch 410 into the L2 latch 412.As shown in FIG. 2, there are three scannable latches 204 seriallycoupled to each other. For scanning the scan-in data 404 into theremaining scannable latches, the next four clock cycles (cycles E-H)repeat the previous four cycles (cycles A-D). On the following fourclock cycles (cycles I-L), as previously mentioned above, the NSL_FCE310 goes high forcing the SDCK 314 to go low on Cycle K. The final orthird scannable latch 204 still performs a scan at clock cycle L so theL2 latch of each of the scannable latches receives the scan data.However, since the SDCK 314 remains low starting at clock cycle K, thescan data is preserved in the L1 latch. Later, at clock cycle P, thefunctional clock (LCK) 312 goes high and destroys the scan datacontained within the L2 latch. The functional clock 312 goes high to doa non-scannable latch fill for the non-scannable latch 206. Next, whilekeeping the SDCK 314 low, the SLCK 316 goes high on clock cycle T andthe scan data preserved in the L1 latch 410 is then scanned into the L2latch 412 for each of the scannable latches. With the scan data scannedinto the L2 at clock cycle T and the non-scannable latch fill performedwhen the functional clock (LCK) 312 goes high at clock cycle P, theinitialization of the scannable latches and a non-scannable latch filloperation is achieved utilizing one local clock buffer 202.

While the illustrative embodiments depicts an L1/L2* configuration of amaster slave scannable latch, one of skill in the art can appreciatethat multiple scannable latch configuration may be used for theteachings herein including other master slave configurations and thelike.

In one or more embodiments, the GCK 302 originates from a clockgenerator which can be any of a single-phase clock, two-phase clock,four phase clock, clock multiplier or the like.

In the illustrated embodiment, the circuit diagram 200 is arranged in aconfiguration that is serial-in/serial-out. However, in one or moreembodiments, the circuit diagram 200 may be arranged in a configurationthat is parallel-in/serial-out, serial-in/parallel-out,parallel-in/parallel-out, and also configured as a ring counter.

FIG. 5 illustrates a block diagram of a method for initializingscannable and non-scannable latches from a common clock buffer accordingto one or more embodiments. The method 500 includes receiving a clocksignal into a local clock buffer, as shown at block 502. Next, at block504, the method 500 includes receiving, at each clock signal, a set ofcontrol signals, the set of control signals including a hold controlsignal, a scan enable control signal, and a non-scannable latch forcecontrol signal. The method 500 next includes responsive to receiving alow input from the hold control signal and the scan enable controlsignal, outputting a high signal from a functional clock port on thelocal clock buffer on a next clock cycle, as shown at block 506. Next,at block 508, the method 500 includes responsive to receiving a highinput from the scan enable control signal and a low input from the holdcontrol signal, outputting a high slave latch scan clock signal on thenext clock cycle. At block 510, the method 500 includes responsive toreceiving a high input from the hold control signal and the scan enablecontrol signal, outputting a high master latch scan clock signal on thenext clock cycle. Next, at block 512, the method 500 includes responsiveto receiving a high input from the non-scannable latch force controlsignal, outputting a low master latch scan clock signal on a currentclock cycle.

Additional processes may also be included. It should be understood thatthe processes depicted in FIG. 5 represent illustrations, and that otherprocesses may be added or existing processes may be removed, modified,or rearranged without departing from the scope and spirit of the presentdisclosure.

Technical effects and benefits include a local clock buffer coupled toboth scannable and non-scannable latches without the need for separatebuffers for each latch type. Most often, different latch types areclocked by different local clock buffers depending on their type,especially for non-scannable and scannable latch types. Removing anextra local clock buffer eliminates the additional power, the additionalchip area, and the additional capacitive load points the extra localclock buffer would need. Also, this eliminates the increased workeffort, the higher power dissipation, the increased chip area, and theless efficient clock connections across the chip that would normally bepresent with the extra clock buffer.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

What is claimed:
 1. A system for initializing scannable andnon-scannable latches from a common clock buffer, the system comprising:a processor, coupled to a memory, configured to perform a method, themethod comprising: receiving a clock signal into a local clock buffer;receiving, at each clock signal, a set of control signals including ahold control signal, a scan enable control signal, and a non-scannablelatch force control signal; responsive to receiving a low input from thehold control signal and the scan enable control signal, outputting ahigh signal from a functional clock port on the local clock buffer on anext clock cycle; responsive to receiving a high input from the scanenable control signal and a low input from the hold control signal,outputting a high slave latch scan clock signal on the next clock cycle;responsive to receiving a high input from the hold control signal andthe scan enable control signal, outputting a high master latch scanclock signal on the next clock cycle; and responsive to receiving a highinput from the non-scannable latch force control signal, outputting alow master latch scan clock signal on a current clock cycle.
 2. Thesystem of claim 1, wherein the local clock buffer is coupled to one ormore scannable latches and at least one non-scannable latch.
 3. Thesystem of claim 1, wherein the hold control signal comprises: anon-scannable latch hold control signal and a scannable latch holdcontrol signal passing through one or more digital logic gates.
 4. Thesystem of claim 3, wherein the one or more digital logic gates is a twoinput AND logic gate with the non-scannable latch hold control signal asa first input and the scannable latch hold control signal as a secondinput.
 5. The system of claim 1, wherein the non-scannable latch forcecontrol signal passes through one or more digital logic gates within thelocal clock buffer.
 6. The system of claim 5, wherein the one or moredigital logic gates is a OR gate with the non-scannable latch forcecontrol signal as a first input and an invert of the scan enable controlsignal as a second input.
 7. A computer program product for initializingscannable and non-scannable latches from a common clock buffer, thecomputer program product comprising a computer readable storage mediumhaving program instructions embodied therewith, wherein the computerreadable storage medium is not a transitory signal per se, the programinstructions executable by a processor to cause the processor to performa method comprising: receiving a clock signal into a local clock buffer;receiving, at each clock signal, a set of control signals including ahold control signal, a scan enable control signal, and a non-scannablelatch force control signal; responsive to receiving a low input from thehold control signal and the scan enable control signal, outputting ahigh signal from a functional clock port on the local clock buffer on anext clock cycle; responsive to receiving a high input from the scanenable control signal and a low input from the hold control signal,outputting a high slave latch scan clock signal on the next clock cycle;responsive to receiving a high input from the hold control signal andthe scan enable control signal, outputting a high master latch scanclock signal on the next clock cycle; and responsive to receiving a highinput from the non-scannable latch force control signal, outputting alow master latch scan clock signal on a current clock cycle.
 8. Thecomputer program product of claim 7, wherein the local clock buffer iscoupled to one or more scannable latches and at least one non-scannablelatch.
 9. The computer program product of claim 7, wherein the holdcontrol signal comprises: a non-scannable latch hold control signal anda scannable latch hold control signal passing through one or moredigital logic gates.
 10. The computer program product of claim 9,wherein the one or more digital logic gates is a two input AND logicgate with the non-scannable latch hold control signal as a first inputand the scannable latch hold control signal as a second input.
 11. Thecomputer program product of claim 7, wherein the non-scannable latchforce control signal passes through one or more digital logic gateswithin the local clock buffer.
 12. The computer program product of claim11, wherein the one or more digital logic gates is a OR gate with thenon-scannable latch force control signal as a first input and an invertof the scan enable control signal as a second input.
 13. The computerprogram product of claim 8, wherein the one or more scannable latchesare master-slave latches comprising a one port master latch and a twoport slave latch.